Applications of VHDL to Circuit Design by Dr. Alec G. Stanculescu (auth.), Randolph E. Harr, Alec G.

By Dr. Alec G. Stanculescu (auth.), Randolph E. Harr, Alec G. Stanculescu (eds.)

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I ,-•••••••••••••• -- -llU--·-- ---- •••• - - ••• j I - ---------- ------ --. -- •• -l1li1- --. ---. --------I I--·---·----------------"Fx--------···········--I 1- --. ------------------ --I 1----- --- --- -- -- - -- --- -- -- -IIrx- -- --- -- -- - -- -- -- -. - ••• --. - + I •••••• _-. -- -------- --- --- -- -- --- __ - . __ . - . __ - - • • - - • • - -_ - - ---n--- -- --- ---- ----- --- --- -. -. -.. 2 Functional Support for the 46-value System This section presents only those functions of the stdJogic package that are explicitly used in this chapter.

Understanding these properties is important when the user has the ability to create new resolution functions, as it is the case in YHDL. The main properties of resolution functions are: Lattice: The values of the value-system can be partially ordered by strength. If the resolution function returns the smallest value that is larger than each of the values it is resolving, the value-system is said to be organized Switch-Level Modeling in VHDL 15 as a lattice. This is an important property for switch· level descriptions.

Ctivations for a particular time point. An internal wakeup signal is used to model the connecting and the disconnecting states. When the wakeup value is false, the process is in a disconnecting state. nged to false after 1 fs inertial delay. The 1 fs inertial delay is to guarantee that there are no events on the sensitivity list of the process, when the wakeup value changes from true to false. In the disconnecting state, the pass transistors remove their driving effects. In the reconnecting state the pass transistors "pass", in both directions, the resolved values of the driving sources.

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