Basic ESD and I/O Design by Sanjay Dabral

By Sanjay Dabral

The 1st accomplished advisor to ESD safety and I/O designBasic ESD and I/O layout is the 1st publication dedicated to ESD (electrostatic discharge) safety and input/output layout. Addressing the turning out to be call for in for high-speed I/O designs, it bridges the space among ESD study and present VLSI layout practices and offers a much-needed reference for training engineers who're usually known as upon to profit the topic at the job.This quantity provides an built-in remedy of ESD, I/O, and technique parameter interactions that either I/O designers and procedure designers can use. It examines key elements in I/O and ESD layout and checking out, and is helping the reader think about ESD and reliability matters up entrance while making I/O offerings. Emphasizing readability and ease, this ebook makes a speciality of layout ideas that may be utilized commonly as this dynamic box keeps to conform.

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If the NMOS is too large compared to that required by the actual I/O driver requirements, then some legs can be tied to a normal off state. • Section the resistor and NMOS into an appropriate number of segments to suit the layout. Of course, using the GCNMOS or the ratioed-gate NMOS (RGNMOS) technique, all the NMOS fingers could be snapped back and ensure better uniformity in ESD current sharing. Another method to increase the ratio of impedances between the NMOS path and the diode path is to utilize a pinch-type resistor in the N-well [Ghandhi, 1983; Orchard-Webb, 1991].

These trigger voltages may be in the 30-60-V range. Thus, the circuit is not protected until the trigger voltages are reached, and then the SCR turns on. Also, it takes an SCR finite time to latch up (...... 1 ns) and the SCR can be too slow for some applications [Diaz, 1994; Duvvury, 1995]. 4. Medium-Voltage'n-iggered SCR (MVTSCR) The nonnal SCR had a high trigger voltage, which leads to poor ESD performance. The MVTSCR is a normal SCR that has been adapted by adding a bridging N+ area between the N-well and P-epi (shown in Figure 2-7) [Duvvury, 1995].

Veep to Vee: The connection between Veep and Vee can also be established by a diode or a diode chain depending on the voltage difference between Veep! and Vcc' Also, the noise isolation between the two supplies should be considered. • Vee to Vs,,: The path between the Vee supply and Vss is provided by the core clamp. This device is nonnally off during circuit operation. During an ESD event it is a low-impedance path and ideally a short. • V ss to Pad: The path between V ss to pad is provided by the parasitic and a designed diode.

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